SISD

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Flynn's taxonomy (multiprogramming context)
	Single instruction stream	Multiple instruction streams	Single program	Multiple programs
Single data stream	SISD	MISD
Multiple data streams	SIMD	MIMD	SPMD	MPMD

In computing, SISD (single instruction stream, single data stream) is a type of computer architecture in which a single uni-core processor, executes a single instruction stream, to operate on data stored in a single memory. This corresponds to the von Neumann architecture.

SISD is one of the four main classifications as defined in Flynn's taxonomy. In this system, classifications are based upon the number of concurrent instructions and data streams present in the computer architecture. According to Michael J. Flynn, SISD can have concurrent processing characteristics. Pipelined processors and superscalar processors are common examples found in most modern SISD computers.^[1]^[2]

References

↑ Quinn, Michael J. Chapter 2: Parallel Architectures, Parallel Programming in C with MPI and OpenMP. Boston: McGraw Hill, 2004. ISBN 0-07-282256-2
↑ Ibaroudene, Djaffer. Chapter 1: Motivation and History, Parallel Processing. St. Mary's University, San Antonio, TX. Spring 2008.

v t e CPU technologies
Architecture	Von Neumann Harvard (Modified Harvard) Dataflow TTA
Instruction set	ASIP CISC RISC EDGE EPIC MISC OISC VLIW NISC ZISC TRIPS Comparison
Word size	1-bit 4-bit 8-bit 9-bit 10-bit 12-bit 15-bit 16-bit 18-bit 22-bit 24-bit 25-bit 26-bit 27-bit 31-bit 32-bit 33-bit 34-bit 36-bit 39-bit 40-bit 48-bit 50-bit 60-bit 64-bit 128-bit 256-bit 512-bit variable
Execution	Instruction pipelining Bubble Operand forwarding Out-of-order execution Register renaming Speculative execution Branch predictor Memory dependence prediction Hazards
Parallel level	Bit Bit-serial Word Instruction Scalar Superscalar Task Thread Process Data Vector Memory
Multithreading	Temporal Simultaneous Preemptive Cooperative
Flynn's taxonomy	SISD SIMD MISD MIMD SPMD Addressing mode
Types	Digital signal processor (DSP) GPGPU Microcontroller Physics processing unit System on a chip (SoC) Cellular
Components	Address generation unit (AGU) Arithmetic logic unit (ALU) Barrel shifter Floating-point unit (FPU) Back-side bus Multiplexer Demultiplexer Registers Memory management unit (MMU) Translation lookaside buffer (TLB) Cache Register file Microcode Control unit Clock rate
Power management	APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating
CPU hardware security	NX bit Hardware restriction (firmware) Trusted Execution Technology Secure cryptoprocessor Hardware security module Hengzhi chip

v t e Parallel computing
General	Distributed computing Cloud computing High-performance computing
Levels	Bit Instruction Task Data Memory
Multithreading	Temporal Simultaneous Preemptive Cooperative
Theory	PRAM model Analysis of parallel algorithms Amdahl's law Gustafson's law Cost efficiency Karp–Flatt metric Slowdown Speedup
Elements	Process Thread Fiber Instruction window
Coordination	Multiprocessing Memory coherency Cache coherency Cache invalidation Barrier Synchronization Application checkpointing
Programming	Models Implicit parallelism Explicit parallelism Concurrency Non-blocking algorithm
Hardware	Flynn's taxonomy SISD SIMD MISD MIMD Pipelined processor Superscalar processor Vector processor Multiprocessor symmetric asymmetric Memory shared distributed distributed shared UMA NUMA COMA Massively parallel computer Computer cluster Grid computer
APIs	POSIX Threads OpenMP OpenCL OpenHMPP OpenACC MPI PVM UPC TBB Boost.Thread Global Arrays Ateji PX Charm++ Cilk Coarray Fortran CUDA Dryad C++ AMP PLINQ TPL
Problems	Embarrassingly parallel Software lockout Scalability Race condition Deadlock Livelock Starvation Deterministic algorithm Parallel slowdown
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